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An FPGA implementation of incremental clustering for radar pulse deinterleaving.

机译:雷达脉冲解交织的增量聚类的FPGA实现。

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摘要

Incremental clustering is the unsupervised classification of dynamic streaming data samples into related groups called clusters. The process considers each data point only once so it is applicable to real-time problems requiring low latency solutions. One such application is the deinterleaving of radar pulse streams in an electronic warfare (EW) systems. Given a single stream of combined radar signals deinterleaving attempts to identify individual radar emitters based on characteristics of the received signal.;This thesis focuses on implementing an incremental clustering algorithm on a field-programmable gate array (FPGA) for the purposes of radar pulse deinterleaving. We introduce ICED, an algorithm for the Incremental Clustering of Evolving Data, and discuss the details of implementing it in an FPGA. Experimental results show the applicability of the algorithm to the real-time requirements of EW pulse deinterleaving. The resulting design provides a 16 cluster implementation that consumes 70% of a Xilinx Virtex-5 SX95T FPGA and requires a processing latency of 420ns, resulting in a 39x speedup over software.
机译:增量聚类是将动态流数据样本无监督地分类为称为聚类的相关组。该过程仅考虑每个数据点一次,因此适用于需要低延迟解决方案的实时问题。一种这样的应用是在电子战(EW)系统中雷达脉冲流的解交织。给定单个组合的雷达信号解交织尝试根据接收信号的特征识别单个雷达发射器。;本文着眼于在现场可编程门阵列(FPGA)上实现增量聚类算法,以实现雷达脉冲解交织。我们介绍了ICED,一种用于不断发展的数据的增量聚类的算法,并讨论了在FPGA中实现它的细节。实验结果表明,该算法适用于电子战脉冲解交织的实时性要求。最终的设计提供了16个集群的实现,消耗了Xilinx Virtex-5 SX95T FPGA的70%,并且需要420ns的处理延迟,从而使软件的处理速度提高了39倍。

著录项

  • 作者

    Bailie, Scott Michael.;

  • 作者单位

    Northeastern University.;

  • 授予单位 Northeastern University.;
  • 学科 Engineering Electronics and Electrical.
  • 学位 M.S.
  • 年度 2010
  • 页码 81 p.
  • 总页数 81
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

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