In direct-conversion receivers, radio frequency (RF) signals are down-converted to zero or low intermediate frequency (IF) using complex in-phase and quadrature (I/Q) mixers with no prior image filtering. Due to I/Q path gain and phase errors, image leaks into the signal band during the down-conversion process. A generic image rejection algorithm is proposed to reject image in the baseband using a zero-forcing sign-sign adaptive feedback concept. The orthonormal property of complex I/Q channels is exploited to update their gain and phase errors by detecting only four signs, and image is corrected with four multiplications and two additions. The correction and detection algorithms can be implemented in a digital or analog form. The analog correction circuit consists of a complex baseband sample and hold (S/H) with trim capacitors. At 40 MS/s sampling rate, the analog, 12-b digital, and hybrid (analog correction and digital detection) image rejection circuits achieve an image rejection of 62, 65, and 65 dB, respectively. The prototype chip fabricated in 0.18-mum CMOS occupies 800 x 450 mum2, and consumes 23 mW at 1.8 V.
展开▼
机译：在直接转换接收器中，使用复杂的同相和正交（I / Q）混频器将射频（RF）信号下变频为零或低中频（IF），而无需事先进行图像滤波。由于I / Q路径增益和相位误差，在下变频过程中图像泄漏到信号带中。提出了一种通用的图像拒绝算法，该算法使用迫零符号-符号自适应反馈概念来拒绝基带中的图像。通过仅检测四个符号来利用复杂I / Q通道的正交特性来更新其增益和相位误差，并通过四个乘法和两个加法来校正图像。校正和检测算法可以以数字或模拟形式实现。模拟校正电路由带有微调电容器的复杂基带采样和保持（S / H）组成。以40 MS / s的采样率，模拟，12位数字和混合（模拟校正和数字检测）图像抑制电路分别实现62、65和65 dB的图像抑制。采用0.18微米CMOS制造的原型芯片占地800 x 450平方毫米，在1.8 V时功耗为23 mW。
展开▼
