Timing Influenced Layout Design

摘要

We present a new approach to the automatic layout design for VLSI chips which incorporates timing information to influence the placement and wiring processes. This approach is an extension of the hierarchical layout method, in which placement and wiring are performed simultaneously [1]. We add a third phase of timing to the hierarchy, without affecting the computational complexity of the basic algorithm. Prior to the physical design, timing analysis is performed using statistical estimates for the unknown parameters; namely the lengths of interconnecting wires. The output of this analysis includes a measure for each net that indicates the degree of its contribution to the timing problem. This set of measures is used to bias the placement at the highest level of the hierarchy. Since wiring is performed after each level of partitioning, lengths of interconnecting nets among the partitions become available. These data are used to update the timing information that bias the design. Preliminary results show that, while delays due to interconnections are reduced, wireability of the chip does not deteriorate.