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Multilayer buffer system for fabrication of high-Tc edge-geometry superconductorormal-metal superconductor (SNS) weak links on silicon-on-sa

机译:用于在buffer上硅上制造高Tc边缘几何超导体/法向金属超导体(SNS)薄弱环节的多层缓冲系统

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Abstract: High frequency detector and circuit applications often require device fabrication on medium-to-low dielectric constant substrates ($epsilon $LS 12). Silicon-on-sapphire (SOS) substrates have acceptably low dielectric constants and provide other important advantages, including the possibility of monolithic integration of silicon and superconducting circuitry. Our initial results with YBa$-2$/Cu$-3$/O$-7$MIN@x$/(YBCO) edge- geometry superconductorormal-metal/superconductor (SNS) weak links fabricated on r-plane SOS substrates using cubic zirconia (YSZ) buffer layers revealed problems with grain boundary nucleation in the YBCO counterelectrode. These results motivated development of a new multilayer buffer system consisting of an epitaxial YSZ film grown on an SOS substrate, overlaid by a thin YBCO 'seed' layer, and an epitaxial SrTiO$-3$/ (STO) layer. STO - YBCO bilayers grown over the YBCO seed layer show a remarkable improvement in epitaxial quality and in YBCO electrical properties relative to similar bilayers grown directly on the YSZ buffer. In addition, SNS weak links fabricated on SOS substrates using the multilayer buffer system exhibit dramatically improved electrical characteristics compared to devices produced on YSZ buffer layers. These are the first epitaxial edge-geometry SNS weak links produced on SOS substrates. !25
机译:摘要:高频检测器和电路应用通常需要在中低介电常数衬底(epsilon $ LS 12)上制造器件。蓝宝石上的硅(SOS)衬底具有可接受的低介电常数,并具有其他重要优势,包括硅与超导电路的单片集成的可能性。我们在Y平面SOS上制作的YBa $ -2 $ / Cu $ -3 $ / O $ -7 $ MIN @ x $ /(YBCO)边缘几何超导体/法向金属/超导体(SNS)薄弱环节的初步结果使用立方氧化锆(YSZ)缓冲层的基板显示YBCO对电极的晶界成核问题。这些结果推动了新的多层缓冲系统的开发,该系统包括在SOS衬底上生长的外延YSZ膜,外延薄的YBCO“种子”层和外延SrTiO $ -3 $ /(STO)层。与直接在YSZ缓冲液上生长的类似双层膜相比,在YBCO种子层上生长的STO-YBCO双层膜在外延质量和YBCO电性能方面显示出显着的改善。此外,与在YSZ缓冲层上生产的器件相比,使用多层缓冲系统在SOS基板上制造的SNS弱连接展现出显着改善的电气特性。这些是在SOS基板上产生的第一个外延边缘几何形状的SNS薄弱环节。 !25

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