Characterization of Global and Local Wafer Shape Change along Through Silicon Via Process Steps

摘要

As demands for high performance and highly functional devices increase, device scaling by continuing miniaturization and alternative three dimensional (3D) packaging techniques are required. As an alternative approach to traditional device scaling, 3D packaging using through silicon vias (TSVs) filled with copper (Cu) is being actively investigated. The development of stress, during various TSV fabrication steps, poses a risk of compromised device performance, reliability and yield loss. We have characterized global and local wafer shape change, along various TSV process integration steps, using a newly developed laser-based wafer surface profiling system. The importance of global (wafer level) and local (chip or die level) profile (flatness, bow and/or distortion) characterization and its contribution to proper understanding of the mechanisms involved in wafer bowing, stress build up and/or pattern overlay problems are discussed.