A High-Performance Digital-Input Class-D Amplifier with Direct Battery Connection in a 90nm Digital CMOS Process

机译：带有90nm数字CMOS工艺的直接电池连接的高性能数字输入D类放大器

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The class-D amplifier system presented in this paper is a second-order architecture that operates on a digital PWM input and eliminates the use of an external carrier signal. It consists of two identical audio channels and a common section consisting of a

机译：本文介绍的D类放大器系统是一种二阶体系结构，可在数字PWM输入上运行，并且无需使用外部载波信号。它由两个相同的音频通道组成，并由一个公共部分组成。

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来源
《Performance Analysis of Systems and Software (ISPASS), 2008 IEEE International Symposium on; San Francisco,CA》||P.436-625|共190页
会议地点 San FranciscoCA
作者
Ramaswamy; S.; Krishnan; J.; Forejt; B.; Joy; J.; Burns; M.; Burra; G.;
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原文格式 PDF
正文语种 eng
中图分类工业技术;
关键词
CMOS digital integrated circuits; amplifiers; delta-sigma modulation; digital filters; phase locked loops; pulse width modulation; PLL; PWM generator; audio channels; digital CMOS process; digital DeltaSigma modulator; digital PWM; digital interpolation filter; exter;

机译：CMOS数字集成电路;放大器;Δ-Σ调制;数字滤波器;锁相环;脉冲宽度调制; PLL; PWM发生器;音频通道;数字CMOS工艺;数字DeltaSigma调制器;数字PWM;数字插值滤波器;外部;

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1. Integrated 105 dB SNR, 0.0031% THD+N Class-D Audio Amplifier With Global Feedback and Digital Control in 55 nm CMOS [J] . Kinyua Martin, Wang Ruopeng, Soenen Eric Solid-State Circuits, IEEE Journal of . 2015,第8期

机译：集成105 dB SNR，0.0031％THD + N D类音频放大器，具有55 nm CMOS的全局反馈和数字控制
2. A 40-nm CMOS, 1.1-V, 101-dB Dynamic-Range, 1.7-mW Continuous-Time src="/images/tex/16713.gif" alt="Sigma Delta "> ADC for a Digital Closed-Loop Class-D Amplifier [J] . Donida Achille, Cellier Remy, Nagari Angelo, Circuits and Systems I: Regular Papers, IEEE Transactions on . 2015,第3期

机译：40纳米CMOS，1.1V，101dB动态范围，1.7mW连续时间<配方公式type =“ inline”> src =“ / images / tex / 16713.gif” alt =“ Sigma Delta “> 用于数字闭环D类放大器的ADC
3. Digitally-Controlled Polar Transmitter Using a Watt-Class Current-Mode Class-D CMOS Power Amplifier and Guanella Reverse Balun for Handset Applications [J] . Nakatani T. Solid-State Circuits, IEEE Journal of . 2012,第5期

机译：使用Watt级电流模式D类CMOS功率放大器和Guanella Reverse Balun进行数字控制的极性发射器，用于手机应用
4. A High-Performance Digital-Input Class-D Amplifier with Direct Battery Connection in a 90nm Digital CMOS Process [C] . Ramaswamy S., Krishnan J., Forejt B., IEEE International Solid-State Circuits Conference . 2008

机译：高性能数码输入类-D放大器，直接电池连接在90nm数字CMOS过程中
5. A 1.5V multirate multibit sigma delta modulator for GSM/WCDMA in a 90nm digital CMOS process. [D] . Altun, Oguz. 2005

机译：适用于GSM / WCDMA的1.5V多速率多比特sigma delta调制器，采用90nm数字CMOS工艺。
6. A High Speed CMOS Image Sensor with a Novel Digital Correlated Double Sampling and a Differential Difference Amplifier [O] . Daehyeok Kim, Jaeyoung Bae, Minkyu Song 2015

机译：具有新型数字相关双采样和差分差动放大器的高速CMOS图像传感器
7. 1Phase Predistortion of a Class-D Outphasing RF Amplifier in 90nm CMOS [O] . Jonas Fritzin, Student Member, Ylva Jung, 2016

机译：在90nm CmOs中的D类异相射频放大器的1相预失真

A High-Performance Digital-Input Class-D Amplifier with Direct Battery Connection in a 90nm Digital CMOS Process

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