Hardware Implementation Study of the Deficit Table Egress Link Scheduling Algorithm

摘要

The provision of Quality of Service (QoS) in computing and communication environments has increasingly focused the attention from academia and industry during the last decades. Some of the current interconnection technologies include hardware support that, adequately used, allows to offer QoS guarantees to the applications. The egress link scheduling algorithm is a key part of that support. Apart from providing a good performance in terms of, for example, good end-to-end delay (also called latency) and fair bandwidth allocation, an ideal scheduling algorithm implemented in a high-performance network with QoS support should satisfy other important property which is to have a low computational and implementation complexity. In this paper, we propose a specific implementation of the DTable scheduling algorithm and show estimates about its complexity in terms of silicon area and computation delay. In order to obtain these estimates, we have performed our own hardware implementation using the Handel-C language and employed the DK design suite tool from Celoxica.