Multi-FPGA systems are used as custom computing machines, logic emulators and rapid prototyping vehicles. A key aspect of these systems is their programmable routing architecture which is the manner in which wires, FPGAs and Field-programmable interconnect Devices are connected. Several routing architectures ofr MFSs have been porposed[Arno92][Butt92][Hauc94][Apti96][Vuil96][Babb97] and previous research has shown that the partial crossbar is one of the best existing architectues [Kim96][khal97]. Recently, the Hybrid complete-Graph Partial-Crossbar architecture was proposed [Khal98], which was shown to be superior to the Partial crossbar. In this paper we propose a new routing architecute, called the hardwired-Clusters partial-Crossbar which si better suited for large MFSs implemented using multiple boards. The HWCP architectue is compared to the HCGP and Partial Crossbar and we show that it gives substantially bettermanufacutrability.We compare the performance and cost of the HWCP, HCGP and Partial Crossbar architecutes experimentally, by mappinga set of 15 large benchmark circuits into each architecture. We show that the HWCP archtiecute gives reasonably good cost and speed compared to the HCGP and Partial Crossbar architectures.
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