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Integrated Block-Processing and Design-Space exploration in Temporal Partitioning for RTR Architectures

机译:RTR架构的时间分区中的集成块处理和设计空间探索

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We present an automated temporal partitioning and design space exploratio metodology that temporally partitions behavior specifications. We propose block-processing in the temporal partitioning framework for reducing the reconfiguration overhead for partitinoed designs. Block-processing is a technique used traditionally in the area of parallel compilers, for increasing the computation speed by processing several inuts siumlaneously. Block-proessing technique has been integrated with task-level design space exploration to achieve designs that justify temporal partitioning of systems. An ILP-based metholology has been proposed to solve this problem. We present experimental results for the discrete cosine Transform(DCT).
机译:我们提出了一种自动的时间分区和设计空间探索方法,它可以对行为规范进行时间分区。我们建议在时间分区框架中进行块处理,以减少分区设计的重新配置开销。块处理是并行编译器领域中传统上使用的一种技术,用于通过同时处理多个inut来提高计算速度。块处理技术已与任务级设计空间探索集成在一起,以实现证明对系统进行时间分区的设计。已经提出了基于ILP的气象学来解决该问题。我们提出离散余弦变换(DCT)的实验结果。

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