EVALUATION OF MECHANISMS INTRODUCED TO IMPROVE PERFORMANCE OF TSVM CACHE

摘要

The Tagged Shared Variable Memory (TSVM) is a concept of the structured shared memory that combines communication with synchronization to make parallel processing more efficient. On a single-chip multiprocessor, the TSVM is realized by dividing a conventional data cache to two portions. The one is the TSVM cache and the other is a general variable cache. To achieve the maximum performance gain, we introduce three methods to the physical TSVM. The first is to construct the dedicated bus for the physical TSVM. The second is to put the TSVM into the L1 data cache that each processor has. The third is to relax the coherence maintenance for the TSVM cache. We evaluate in detail additional effects due to the above mechanisms using the simulator of a single-chip multiprocessor with the TSVM cache. The results show that constructing the dedicated bus improves a performance of 0.01 to 38.38%, distributing TSVM cache achieves a performance gain of 2.10 to 34.34%, and relaxing the coherence maintenance improves a performance of 3.55 to 24.08%. Consequently, introduced three methods yield a total performance improvement of 10.54 to 77.38%.