A SCALABLE SEMI-SHARED MEMORY MULTIPROCESSOR ARCHITECTURE WITH SLIDING CACHES

摘要

This paper presents a scalable multiprocessor architecture with sliding caches. The parallel architecture with more intelligent memory model and efficient interconnection network organisation is called as semi-shared memory multiprocessor system. The memory model provides concurrent memory accesses and more memory bandwidth for a scalable semi-shared memory multiprocessor system. In this study, conventional shared, distributed memory multiprocessor and the semi-shared multiprocessor memory are examined under various conditions. These parallel computing models are also compared with each other. Sliding cache memory model are simulated to reduce the cost of the semi-shared memory model. Simulation results of the sliding cache memory shows that memory requirements of a semi-shared memory multiprocessor system is almost independent of scale of the multiprocessor. These results show that the semi-shared memory multiprocessor system with special interconnection network and intelligent memory organisation provides very high speed-up and efficiency over conventional shared and the distributed memory multiprocessor. Therefore, semi-shared memory multiprocessor system with the memory organisation is a potential candidate for large-scale parallel computing applications.