Characterization of snap-back breakdown and its temperature dependence up to 300 degrees C including circuit-level model and simulation

摘要

Abstract: The MOS snap-back phenomenon and its temperature dependence were investigated up to 300 degrees C by measurement, parameter extraction and simulation using silicided LDD-NMOS transistors. The snap-back sustaining voltage increases from 8.25V at room temperature to 8.9V at 300 degrees C. By using extracted parameters for a simple lumped element model we explain this behavior originating from an increasing avalanche breakdown voltage and increasing exponential slope of avalanche multiplication factor compensating the increase in bipolar gain with temperature. The simulation of IV- curves on circuit level using PSPICE shows an acceptable matching to the measured IV-curves. If the extracted parameters describing snap back would be specified in process documents, circuit designers could use them to identify and solve problems related to both ESD protection circuits and EOS. The results are also relevant for high temperature operation of electronics, which is a performance issue of growing importance. !26