Abstract: Deep submicron technology poses many difficult challenges. One of them is the optimization of the clock rate versus sub-threshold leakage trade-off. Top speed performance demands the shortest possible channel length for all transistors in the critical paths, while the need to limit subthreshold leakage requires that no transistor violates the minimum channel length rule. The problem is that the channel length is impacted by the layout density. One cause of variations in channel length is lithography. Since the global lithography settings must be chosen to avoid excessive subthreshold leakage, some of the transistors will have non-minimum channel lengths, and therefore will be slower than necessary. It is possible to compensate for the above effect by resizing transistors on the mask. In this paper we propose a methodology for analyzing different correction schemes in terms of their impact on critical path delays. Our methodology involves transistor categorization according to local layout patterns, together with simulation-based computations of channel length as a function of the local layout pattern. A DRC-based approach is used to identify transistor categories. Lithography simulation is used for proximity effect evaluation. Circuit speed is estimated by critical path simulation. In the paper we will compare various correction schemes for one of the main functional blocks in a a state-of-the-art microprocessor. !12
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