A Compact and Fast Division Architecture for a Finite Field GF(2~m)

摘要

Division over a finite field GF(2~m) is the most time and area consuming operation. In this paper, A new division architecture for GF(2~m) using the standard basis representation is proposed. Based on a modified version of the binary extended greatest common divisor (GCD) algorithm, we design a compact and fast divider. The proposed divider can produce division results at a rate of one per 2m - 1 clock cycles. Analysis shows that the computational delay time of the proposed architecture is significantly less than previously proposed dividers with reduced transistor counts. Furthermore, since the new architecture does not restrict the choice of irreducible polynomials and has the features of regularity and modularity, it provides a high flexibility and scalability with respect to the field size m.