This paper describes the design and implementation of 3D Haar wavelet transform (HWT) with transpose based computation and dynamic partial reconfiguration (DPR). As a result of the separability property of the multi-dimensional HWT, the proposed architecture has been implemented using a cascade of three N-point 1D HWT and two transpose memory for a 3D volume of N × N × N, suitable for 3D medical image compression. The proposed 3D HWT architectures were implemented on Xilinx Virtex-5 field programmable gate array (FPGA) using VHDL. An in-depth performance analysis and comparison has shown that DPR based implementation improves both speed and power consumption as well as reducing the hardware required for the system.
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