Chip level layout and bias considerations for preventing neighboring I/O cell interaction-induced latch-up and inter-power supply latch-up in advanced CMOS technologies

摘要

In future SOC and NOC applications, with mixed voltages on a common chip, and with technology scaling, CMOS latch-up issues will increase between adjacent I/O cells, non-equal power rails, and for sub-function to sub-function and device-to-device situations. With 0.13 and sub-0.13 μm technologies, new latch-up rules will be needed to address high level sub-function integration issues.