WAFER →WLCSP → MULTI-DIE CSP FABRICATION AND USE OF WAFER LEVEL CHIP SCALE PACKAGING

摘要

A customer of our company came to us with a requirement for a 64Mb×72 DDR1 DRAM module. Their maximum available space was 32mm square. This requirement presented several design and assembly challenges. Given the required MCM organization and the available die formats, we discovered that nine (9) die would be required. The smallest of the available die at the time would not fit in the available space without stacking. Our first approach was to stack two die on each of the substrate corners and assembly one die in the middle of the substrate. The bottom die in the stack would be flip chip attached and the top die mounted onto the back side of the bottom die and wire bonded to the substrate. The middle die would be flip chip mounted. This presented test problems. If each die is not tested at speed and burned in, MCM initial yield will be lower than acceptable as will the MCM infant mortality. Fortunately after first article build buy before production started, another semiconductor manufacturer released a physically smaller die in the correct configuration that enabled flip chip assembly of all nine die into a 25mm×32mm area without stacking. We then chose to format the die as WLCSP to allow individual die test and burn-in prior to MCM assembly. This paper details this effort from wafer procurement through MCM assembly.