Study of effects of high-k dielectrics in Schottky Tunneling Source MOSFETs

摘要

The Asymmetric Schottky Tunneling Source SOI-MOSFET (STSFET) is a promising device alternative for future nanometer-scale technology. The device has been modeled and simulated using TCAD SYNOPSYS tool. This paper presents a detailed study of device structure, design and characteristics of both p-type and n-type Asymmetric Schottky Tunneling Source SOI-MOSFETs. The important parameters of the device are schottky barrier height and gate oxide thickness. With the metallic (silicide) source / drain regions, schottky barriers are formed at the source/silicon and drain/silicon junctions. The schottky barrier height can be controlled by applying voltage at the gate. The optimized device shows excellent short channel immunity compared to conventional MOSFETs which helps to improve the scalability and output resistance of the device. The asymmetric nature of the device helps to improve the linear characteristics of the device.