Design and Simulation of A 512 x 1 Readout Circuit for Focal Plane Array

摘要

A CMOS 512×1 readout integrated circuit (ROIC) for an IR focal-plane-array (FPA) has been designed. The pixel pitch is 25um, The input stage is the capacitance trans-resistance amplifier (CTIA) and a correlated double sampling (CDS) circuit is included in each unit. In order to avoid the waste of the threshold voltage in the process of sampling, a matched CMOS sample switch was used in CDS. The simulation results show that, if the output voltage of the preamplifier decreases during the integration process, using pMOS source follower can achieve the maximal output swing. Since the 512 elements shared one output channel, the readout rate was limited due to the large capacitance at the output node. So an off-chip changeable resistance was chosen as the load of the source follower to balance the gain and speed. The timing diagram of the driving signals was presented and discussed. Finally, the simulation results are presented, using Cadence spectreS. The saturated differential output swing is 2.1V at 1MHz pixel readout rate, under the condition of 2.5V reference voltage and a 10kΩ load.