High Speed Low Power VLSI Architecture for SPST Adder Using Modified Carry Look Ahead Adder

摘要

Now a day various techniques have been developed for reducing the power consumption of VLSI designs, such as pipelining and parallel processing, reducing the dynamic power, voltage scaling, clock gating etc. To increase the processing speed of the silicon IC, logic gates are made using CNT FETs and designed using the VLSI technology. Lowering down the power consumption and enhancing the processing speed of IC designs are undoubtedly the two important design challenges in designing ICs. The objective of a paper is to provide, high speed and low power adder. In this paper, a VLSI designed low power; high speed adder is proposed using the SPST approach. This adder is designed by applying the Spurious Power Suppression Technique (SPST) on a modified Carry look ahead adder, which is controlled by a detection unit using an AND gate. The proposed architecture is synthesized. In Xilinx RTL, chip XC5VLX50TFF1165 Vertex 5 series is selected for benchmarking. The timing report shows that to perform 16 bit addition the minimum period required for CLA adder is 14.685 ns and MCLA adder requires 10.003 ns. The proposed adder requires 9.147 ns. An improvement of 37.71% is achieved in speed when compared to SPST with CLA adder and an improvement of 9.147% is achieved in speed when compared to CLA SPST with MCLA adder. The SPST adder implementation with AND gates have an extremely high flexibility on adjusting the data asserting time. This facilitates the robustness of SPST can attain 30% speed improvement.