The Development of Wafer-Level 3D High-Density Junction Capacitor for Passive Device Integration in SiP

摘要

Rapidly growing performance and mixed-signal integration is driving the requirement for product and component miniaturization in electronics applications. Embedded passive technology is a potentially attractive solution to replace discrete passives, due to low parasitic parameters, homogeneous integration and small form factor. Embedded capacitors are widely used in a broad range of applications including filtering, tuning and power-bus decoupling in the substrate. In this paper, Micro-Electron-Mechanical System (MEMS) process based on silicon 3D patterns etching and thermal diffusion doping of silicon is used to fabricate a high-density silicon-embedded capacitor. Deep 3D trench structures formed by the Bosch process in inductively coupled plasma (ICP) increase the effective capacitance area, thus enhancing the capacitance areal density. This paper reports on the fabrication process and electrical properties of silicon trench capacitors and achievable capacitance densities. Measurement results indicate that the 3D-structured capacitor can attain a capacitance density of 12nF/mm~2, which is 10-12 times larger than that of planar semiconductor capacitors. This type of capacitor is a good candidate for high-power decoupling, filtering, and electrostatic discharge (ESD) protection, and may be preferred over SMT capacitors in electronics applications with form factor requirements.