PERFORMANCE INCREASE OF ERROR CONTROL OPERATION ON DATA TRANSMISSION

摘要

In this paper a new approach is proposed to increase the performance of the operation of error control on data transmission. Specifically, a hardware structure for parallel Cyclic Redundancy Check (CRC) calculation is developed to speed up the error control operation of data transmission. Based on a study of the properties of both CRC and Check Sum (CS) a new error detecting scheme is developed which combines CRC and CS. Also it is shown that the proposed error detecting scheme ensures high reliability and performance of the error control operation on data transmission in comparison to CRC alone.