CMOS Characterization/Metrology Challenges for the Lab to the Fab

摘要

Due to a multitude of technological advances identified and implemented since 1963 (the year the CMOS patent was filed), CMOS device fabrication has moved to within the realm of atomic scale engineering. Indeed, moving beyond the classical Dennard scaling regime (<130nm) to finFETs required the introduction of additional technologies such as strain, HKMGs, and a move from planar toward 3D structure. As a result, characterization/ metrology of a multitude of solid state properties is now required. Examples of some of the properties of interest include: Structural dimensions, surface roughness, surface/interface chemistry, film composition, distributions of dopants and other minor/trace elements, bonding, phase, grain size, crystal orientation, strain, etc.