CONTACT INTERCONNECT CHALLENGE AND RESOLUTION PART 2: CABLE AND CONNECTOR CONTACT INTERCONNECT INTEGRITY IN ENTERPRISE SERVER FOR DATA CENTER APPLICATION

摘要

This article is Part 2 of a series of studies on new generation of electronic contact challenges and component interconnects technology for high-end computer products. These products include computer server and data storage for cloud computing applications at the Data Center as well as core routers for service providers, edge and branch routers for enterprise networking companies, and small switch and wireless router for commercial and small and home office. All these cloud computing products require high data speed in terabytes per second and high signal integrity for the massive mobile users and IoT application whenever and wherever users wish to connect. To achieve such mobility and signal integrity, the major focus is to see electrical interconnections between the CPU/GPU and component and contact interconnect between PSU and MB header in the system. Due to the large number of edge-card connections such as DIMM, PCIe, etc. are designed into modern computer systems, in Part 1 of the study a new generation of dual-contact interconnect methodology, component level contact configuration, and interconnect reliability were assessed. The study concluded that particulate control and management serve a good purpose to provide a clean contact interface but this effort is not able to remove the last few thousands of DPPM of DIMM re-seating fallout in manufacturing. Contact performance in insertion loss and return loss due to impedance difference are much less in dual-contact mechanism vs. single-contact due to larger normal force and smaller variation in characteristic impedance. SEM on dual-contact connector and module system indicates both contacts are firmed in contact with module so that there is no chance the intended dual-contact is going to break down to a single-contact mechanism. The plating morphology study show excellent surface quality and uniformity. There is no sign of pin hole as compare to other with much rough granular finish. The logic is that the smaller Palladium molecular can possibly better fit into between Ni and Au metallic structure. The purpose of current study is to look into a critical issue of PSU (Power Supplier Unit) de-asserted event due to intermittent connection between PSU and mother board header (thereafter MB header). In some event, the functionality of the host is switching from contact de-asserts to re-asserts but some just de-asserts and never recover due to various factors. Initial investigation confirmed contact interconnection of both the header and PSU electrical are solid although the problem occurs at the communication between mother board and PSU: BMC can't get PSU sensor reading through PSMI (Power Supply Management Interface) bus due to signal integrity issue. The PSU connects MB through a PSMI cable. First, sequential diagnosis is performed by using multi-meter to confirm connection resistances between PSU and MB were lower than few Ohm which imply level of resistance doesn't impact the PSMI communication. Then individual measurements of PSMI cable and MB header including physical dimensions and contact plating thickness and uniformity are conducted. Furthermore, contact resistances between PSMI cable and MB header were measured by milliohm meter. Measurement found the contact resistance between PSMI cable and MB header vary in a large scale which mean the connection between PSMI cable and MB header is not stable. Then extensive contact variables such as contact impedance, mating and un-mating forces of Multiple PSMI cables with different connectors and MB headers from various vendors are assessed.