Generating VHDL-AMS Models of Digital-to-Analogue Converters From MATLAB庐/SIMULINK庐

摘要

Today, the trend within the electronics industry is for the use of rapid and advanced simulation methodologies in association with synthesis toolsets. This paper presents an approach developed to support mixed-signal circuit design and analysis. The methodology proposed shows a novel approach to the problem of developing behvioural model descriptions of mixed-signal circuit topologies, by construction of a set of subsystems, that supports the automated mapping of MATLAB庐/SIMULINK庐 models to structural VHDL-AMS descriptions. The tool developed, named MS2SV, reads a SIMULINK庐 model file and translates it to a structural VHDL-AMS code. It also creates the file structure required to simulate the translated model in the SystemVision驴. To validate the methodology and the developed program, the DAC08, AD7524 and AD5450 data converters were studied and initially modelled in MATLAB庐/SIMULINK庐. The VHDL-AMS code generated automatically by MS2SV, (MATLAB庐/SIMULINK庐 to SystemVision驴), was then simulated in the SystemVision驴. The simulation results show that the proposed approach, which is based on VHDL-AMS descriptions of the original model library elements, allows for the behavioural level simulation of complex mixed-signal circuits.