A 64 * 64 CMOS digital pixel array based on pulse-width analog-to-digital conversion with on-chip linearizing circuit

摘要

This paper describes a 64 * 64 digital pixel array employing a pulse width analogue to digital conversion scheme. Each pixel contains a photodiode sensor, comparator and memory, and in conjuction with a central control circuit performs the analogue to digital conversion, by timing a pulse generated by the photodiode/comparator circuit. The control circuit produces data which compensates for this nonlinear relationship, resulting in a pixel parallel ADC operation. The digital image data can be read from the array non-destructively, with random access. The array is constructed in a standard 0.35 μm, 3.3 V digital CMOS process.