GOALI: Interconnect Processing Enhancement by Measurement of Nanoscale Dielectric Constant Degradation and Development of Experimentally Verified Models of Nanoscale Deformation

摘要

In the late 1980's, semiconductor manufacturers recognized that the interconnect lines would be the primary source of signal propagation delay as the feature size was reduced below 1 μm. At that time, interconnects were fabricated by subtractive metal etching of Al followed by overlay with a silicon oxide dielectric. Since the interconnect delay is proportional to the product of the resistance and capacitance (RC), interconnect designers elected to use a lower resistivity metal, Cu, and began an extensive development effort to design new dielectric materials with dielectric constants lower than the k～4.3 associated with the TEOS-derived silicon oxide dielectric.