Copper electroplating for on-chip metallization

摘要

Copper electroplating processes for filling sub-0.5 mu m trenches and vias with very high aspect ratios (>4:1) were developed. Copper was electroplated on sputtered Cu seed layer with Ta (or TaN) diffusion barrier. An enhanced Cu deposition at the bottom of trenches/vias and defect-free filling sub-0.5 mu m trenches (down to 0.25 mu m width) of high aspect ratio (up to 4:1) were achieved. Large grains occupying the entire trench were observed. Bottom step coverage of electroplated copper in sub-0.5 mu m trenches was estimated to be about 140percent, while sidewalls step coverage was about 120percent. Via resistance for sub-0.5 mu m vias was measured to be below 0.55 OMEGA . Strong <111> texture, large grains, and low tensile stress were observed in electroplated Cu films and in-laid Cu lines after low temperature anneal.