The Impact of Gate Underlap on Analog and RF Performance of Hetero-Junction FET

摘要

Due to enhanced carrier mobility, InP/InGaAs heterostructure double gate MOSFET evinced himself as an attractive candidate for applications in high performance digital logic circuits. In this paper, our aim was to analyze the impact of gate underlap on analog and RF performance of InP/InGaAs hetero-junction FET using TCAD device simulator. The analog and RF parameters of HFET such as drain resistance (Ro), transconductance (gm), and unity-gain cutoff frequency (fT) are studied for varying underlap length raging from 2 to 9 nm. It is shown that the analog and RF performance of hetero-junction FET is severely affected by amount of underlap and this effect can be moderated by an optimal underlap, which yields a trade-off between the analog and RF performance.