Validation of Pipelined Double-precision Floating Point operations in a multi-core environment implemented on FPGA using the ForSyDe/NoC system generator tool suite

摘要

Testing HW IP Blocks in multi-core environments is difficult. This paper presents a case study where a SINE/COSINE implementation using Pipelined Double-precision operations is implemented in one node, and results are sent through the NoC to a target node for inspection. The purpose of the experiments are two-fold, a) to study how debugging in a multi-core environment can be done and b) to examine why the original SINE/COSINE implementation is generating wrong results. During the experiments, several test-methods are applied to validate the implementations until the Floating Point implementation are generating correct values. After eliminating all faults in the operations, the SINE/COSINE function still generates some residual algorithmic errors, coming from the way the function was implemented. However, the experiments show that these errors can be eliminated with the help of some simple trigonometric rules.