fault tolerance; integrated circuit reliability; network routing; network-on-chip; NoC reliability; deep sub-micron technology; distributed routing algorithm; fault tolerant routing implementation mechanism; irregular 2D mesh NoC; logic based on-chip; many core designs; network-on-chip; routing table; Fault tolerance; Network topology; Ports (Computers); Routing; Switches; System recovery; Topology; Networks-on-chip; implementation; logic based;
机译:2D网格NOCS的容错与拥塞平衡路由算法
机译:二维网状NoC可重构容错路由算法的生成与性能评估
机译:二维不规则网格片上网络的基于区域的容错路由算法
机译:不规则2D网格NoC的容错路由实现机制
机译:3D-Nocs高性能和容错路由算法的设计与评估
机译:圆环中的群集容错路由
机译:二维网状NoC可重构容错路由算法的生成与性能评估