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A 9-bit 1-MS/s 7-μW SAR ADC for ultra low power radio

机译:用于超低功率无线电的9位1-MS / S 7-μWSAR ADC

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A 9-bit 1-MS/s successive-approximation (SAR) analog-to-digital converter (ADC) for ultra low power radio applications using 130 nm CMOS is presented. The ADC achieves a power consumption of 7/μW according to simulation results. This ultra low power is realized by employing a maximally simplified ADC architecture that consists of a dynamic latch comparator, a charge redistribution digital-to-analog converter (DAC), and a SAR logic block based on transmission gate flip-flops. Working at a supply voltage of 0.8 V, the SAR ADC achieves a FOM of 15 fJ/conversion.
机译:提出了一种用于使用130nm CMOS的超低功率无线电应用的9位1-MS / S连续近似(SAR)模数转换器(ADC)。根据仿真结果,ADC实现了7 /μW的功耗。通过采用由动态锁存器比较器的最大简化的ADC架构,电荷再分布式数模转换器(DAC)和基于传输门触发器的SAR逻辑块来实现这一超低功率。在0.8V的电源电压下工作,SAR ADC实现了15个FJ /转换的FOM。

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