A 2.1 μW 76 dB SNDR DT-△∑ Modulator for Medical Implant Devices

摘要

This paper presents a low-power 2~(nd)-order discrete-time (DT) △∑ analog-to-digital converter (ADC) aimed for medical implant devices. The designed △∑ modulator with two active integrators (filters) employs power-efficient two-stage load-compensated OTAs with minimal load and rail-to-rail output swing, which provides higher power-efficiency than the two-stage Miller OTA. The modulator, implemented in a 65nm CMOS technology with a core area of 0.033 mm~2, achieves 76-dB peak SNDR over a 500 Hz signal bandwidth, while consuming 2.1 μW from a 0.9 V supply voltage. Compared to previously reported modulators for such signal bandwidths, the achieved performance (FOM of 0.4 pJ/step) make the presented modulator one of the best among sub-l-V modulators in term of most commonly used figure of merit.