LOW COST AND EFFECTIVE IMD PLANARIZATION USING CMP AND RESIST ETCHBACK

摘要

In order to overcome CMP polishing problems related to the Pre-CMP dielectric step height variation, we make use of the Resist Etchback Approach to reduce the step height variation across the wafer prior to the CMP process. This method of planarization-aid significantly reduced the processing cost by eliminating the reverse masking step that is required for each IMD layer. In general, this method makes use of the non-conformal property of the spin-on photo resist (PR), where the large-step-height features will have thinner PR coated as compared to those with small-step-height. In this way, the blanket RIE etch process can be controlled in such a way that once the PR on top of the large-step-height features is cleared, the etch chemistry will be changed to etch the exposed oxide; while the small-step-height features (i.e. recess region) are still protected by PR. Hence, with the use of the Resist Etchback scheme, the Pre-CMP oxide step height can be effectively reduced even without the use of reverse mask. However, the main disadvantage of this planarization-aid is that the degree of planarization by the etchback process is dependent on the metallization line width.