【24h】

A New Trench-Planner Gate MOSFET Structure

机译:一种新的沟槽策划门MOSFET结构

获取原文

摘要

A new trench-planar gate MOSFET (TPMOS) structure is proposed, in which the shallow trench filled with n-type polysilicon is located at the center of n~- drift region between two p-type regions. Compared with conventional VDMOS, the new structure's on-resistance can reduce about 25%, the breakdown voltage can increase 10% and switching loss can retain immovability. Furthermore, the shallow trench structure can be realized by the existing etching process, and retains the advantage of simple technology and low cost. So it can further meet the need of higher voltage power switches application.
机译:提出了一种新的沟槽平面栅极MOSFET(TPMOS)结构,其中填充有n型多晶硅的浅沟槽位于两个p型区域之间的N〜漂移区域的中心。与传统的VDMOS相比,新的结构的导通电阻可以减少约25%,击穿电压可以增加10%,开关损耗可以保持不可疏松性。此外,浅沟槽结构可以通过现有的蚀刻工艺实现,并保留简单技术和低成本的优点。因此,它可以进一步满足更高电压电源开关的需要。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号