Empirical study of identifying gaps between users expectation and experience in the verification methodologies of semiconductor industry

摘要

Independent of the application field, major factors in focus when using the products are quality, cost and time. Empirical studies have shown that in IC design projects as much as half of the projected schedule is spent on the verification activities. Our research work involved exploring the current state of practice of the verification process, investigating methods for achieving efficient fault detection during the product verification, implementation of accumulated knowledge and techniques for efficient verification in one real-world practical case and analysing the impact of the current verification process in terms of time, cost and quality of product verification. This paper covers the views of verification experts in semiconductor industry on latest verification techniques. It shows the most commonly used verification improvement activities that had been implemented by semiconductor companies and its impact on quality, cost and time of the products. The methodology encompassed survey and semi-structured interviews at VLSI companies. Experiments were done to evaluate the new verification methods before using them in real projects. This paper is mainly focussed on identifying the gaps between the expectation of the verification experts and their real experiences of latest verification techniques for product verification process in semiconductor industry.