An on-chip integrated III–V / CMOS 125MSps 6-bit SAR ADC

摘要

This paper presents a fully integrated on-chip III-V HEMT and CMOS hybrid technology, implementing a 6b 125MSps successive approximation register (SAR) ADC. On-chip integration is achieved by using a hybrid PDK that permits direct integration of Au-free III-V devices into a foundry-proven CMOS process. The prototype utilizes an on-chip integrated InGaAs sampling switch and remaining circuits in CMOS. A “more than Moore” design and fabrication methodology has been adopted to overcome CMOS performance limitation. On-chip InGaAs switch integration results in reduction of parasitic elements, enhance the settling speed and superior dynamic performance. In this work the ADC consumes 1.99mW from a 1.8V supply achieving 33.7dB SNDR at nyquist and occupies 0.0225mm2.