Effect of process parameter variability on the threshold voltage of downscaled 22nm PMOS using taguchi method

摘要

This paper provides the enhancement of 22nm planar PMOS transistor technology through downscaling, design parameter simulation and optimization process. The scaled down device is optimized for its process parameter variability using Taguchi method. The aim is to find the best combination of fabrication parameters in order to achieve the target value of the threshold voltage (V). A combination of high permittivity material (high-k) and metal gate is utilized simultaneously in replacing the conventional SiO/Poly-Si technology. For this, Titanium dioxide (TiO) was used as the high-k material and tungsten silicide (WSi) was used as the metal gate. The simulation results show that the optimal threshold voltage (V) of −0.289 V ± 12.7% is achieved in accordance to the ITRS 2012 specifications. This provides a benchmark towards the fabrication of 22 nm planar PMOS in future work.