Critical-path aware power consumption optimization methodology (CAPCOM) using mixed-VTH cells for low-power SOC designs

摘要

In this paper, a critical-path aware power consumption optimization (CAPCOM) using mixed-VTH cells for low-power SOC designs is presented. Using the critical-path weighted sensitivity as an index for assigning each cell to LVT, HVT or MVT, the CAPCOM provides an effective power saving for a low-volt/ low-power SOC design, as indicated in a 16-bit multiplier circuit with 3811 logic cells using a 90nm CMOS technology at 1V with a 44.9% reduction in power consumption as compared to the MVTCMOS technique using all-LVT cells.