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Pre-designed Prognostic cells for host circuits reliability monitoring

机译:预先设计的用于主机电路可靠性监控的预测单元

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CMOS integrated circuits have certain defined failure mechanisms that can contribute to end-of-life failure. These failure mechanisms include time dependent dielectric breakdown, electromigration, hot carrier injection and so on. All of these common failure modes are far worse at geometries below 0.18 µm. The traditional reliability predictions for integrated circuits are inaccurate because they do not account for the actual environments that the circuits are subjected to in its life cycle. Prognostics is a method that enables monitoring the state of reliability of a product in real time, and therefore can be used to provide advance warning of a failure, to provide condition based maintenance and to help in IC design and development. Pre-designed Prognostic cells are incorporated into integrated circuits to provide advance warning of failure for specific wear-out failure mechanisms. The time to failure of these prognostic cells can be pre-calibrated with respect to the time to failure of the host circuit. The accurate failure prediction and the remaining luseful life for specfic failure mechanism were achieved from the prognostic cell with the proper prognostic distance.
机译:CMOS集成电路具有某些已定义的故障机制,这些机制可能会导致使用寿命终止故障。这些故障机制包括与时间有关的介电击穿,电迁移,热载流子注入等。所有这些常见的故障模式在几何尺寸低于0.18 µm时都更加糟糕。集成电路的传统可靠性预测是不准确的,因为它们没有考虑电路在其生命周期中所经受的实际环境。预测是一种能够实时监视产品可靠性状态的方法,因此可用于提供故障预警,提供基于状况的维护并帮助IC设计和开发。预先设计的预后单元已集成到集成电路中,以针对特定的磨损故障机制提供故障预警。这些预后细胞的失效时间可以相对于主机电路的失效时间进行预先校准。准确的故障预测和特定故障机制的剩余有效寿命是从具有适当预后距离的预后细胞中获得的。

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