PACKAGE-ON-PACKAGE (PoP) ASSEMBLY CHALLENGES AND SOLUTIONS FOR LOW-VOLUME ENGINEERING PROTOTYPE AND TEST APPLICATIONS

摘要

Today's package-on-package (PoP) solutions are pervasive in handset and other small form-factor consumer products. Typical current high-volume PoP production assembly flows are set up to build the pretested top and bottom devices using flux or paste dipping stations to stack the individually packaged devices and then reflow the complete board assembly in one pass. Engineering test builds, typically used for process development, thermal/mechanical/electrical characterization purposes, and the like, typically require quantities of a few 10s-100s of assemblies with many possible different combinations of substrates, dice, and test boards. Builds for OSAT and EMS process development usually require near production-like assembly flows to prove-out yield and reliability; however, PoP assemblies for electrical and thermal test/ characterization do not often require an exact production process flow. The early test silicon can be from un-probed, blind-build wafers. Therefore the assembled PoP devices may need to be removed and replaced several times on small form-factor handset-sized or other test/characterization boards. Flexible assembly and test solutions are important in these applications.The typical high-volume PoP assembly methods are not always flexible enough for low-volume engineering test applications that may have several different part mixes. This paper will review example solutions to enable small-lot batch assemblies using conventional laminate glass-epoxy substrates with wirebond test silicon. The PoP assembly of reference is an industry standard, 12×12 mm body, 0.65mm BGA pitch, two-device stack configuration. These particular assemblies were used for high frequency SI and PI electrical characterization purposes. Included in the paper are summaries of the two package substrate designs, die attach configuration, solder pad/ball configurations, encapsulation, pre-stacked reflow operations, and X-ray inspection methods. The application of a 12×12mm solder-down, miniature test socket will also be reviewed. Its use permits multiple PoP devices to be tested on a single, small form-factor characterization board without multiple solder reflow cycles.