built-in self test; SRAM chips; DRAM chips; boundary scan testing; integrated circuit interconnections; integrated circuit testing; design for testability; logic testing; at-speed interconnect test; at-speed interconnect diagnosis; external memories; built-in self test; double data rate; quad data rate; SRAM; fast cycle RAM; reduced latency DRAM; fixed latency memory controller; functional interface protocols; handshake memory controllers; BIST architecture; boundary scan driven BIST operation; system level test; system level diagnosis; system clock; system hard reset; soft reset; BIST functions; system mission operation; design for testability;
机译:逻辑堆叠的3-D存储器的绑定后互连测试和诊断
机译:使用低速和低内存测试仪诊断全速扫描BIST电路
机译:逻辑BIST加速器(LBA):用于大型系统级芯片的全速测试的关键设备
机译:在系统上的外部存储器的速度互连测试和诊断
机译:可重新配置的设备互连测试和诊断时间减少了。
机译:韩国与诊断相关的新小组报销系统和实验室测试质量:外部质量评估结果的分析
机译:具有多个系统时钟的电路板中的速度边界扫描互连测试