20 GFLOPS QR processor on a Xilinx Virtex-E FPGA

摘要

Adaptive beamforming can play an important role in sensor array systems in countering directional interference. In high-sample rate systems, such as radar and comms, the calculation of adaptive weights is a very computational task that requries highly parallel solutions. For systems where low power consumption and volume are improtant the only viable implementation is as an Application Specific Integrated Circit (ASIC). However, the rapid advancement of FIeld Programmable Gate Array (FPGA) technology is enabling highly credible re-programable solutions. In this paper we present the implementation of a scalable linear array processor for weight calculation using QR decomposition. We employ floating-point arthmetic with mantissa size optimised to the target application to minimise component size, and implement them as relationally placed macros (RPMs) on Xilinx Virtex FPGAs to achieve predictable dense alyot and high-speed operation. We present results that show that 20GFLOPS os usstained computation on a single XCV3200E-8 Virtex-E FPGA is possible. We also describe the parameterises implementation of the floating-point operators and QR-processor, and the design methodology that enables us to rapidly generate complex FPGA implemenations using the industry standard hardware description language VHDL.