Systematic methodology for optimizing the tradeoff of polysilicon depletion versus boron penetration in sub-0.18-um surface-channel PMOS devices

摘要

Control of boron penetration in surface-channel PMOS devices is critical in order to ensure tight threshold voltage (V$- t$/) distribution. Previous work has focused on studying relatively gross boron-penetration effects, which give rise to large shifts in V$-t$/. In practice, low-voltage CMOS technologies are sensitive to small degradation in PMOS V$- t$/ scatter due to the onset of boron penetration. Moreover, the use of rapid thermal annealing can give rise to difficult trade-offs between poly depletion and boron penetration. As both of these effects can influence the PMOS V$-t$/ we propose a sensitive, systematic, methodology to distinguish between depletion and penetration effects and illustrate its application in a number of advanced CMOS processes, with oxide thickness ranging from 30-50 angstrom.