Coarse Grained versus Fine Grained Architectures for Asynchronous Reconfigurable Devices

摘要

This paper proposes a specialized coarse grained architecture for the communication functions of reconfigurable devices in globally asynchronous locally synchronous systems. Our configurable logic block includes four 40-bit data registers that can be configured as MOUSETRAP pipeline stages, and 10—15 times more look-up tables/flip-flops than the typical conventional fine grained architecture. Dedicated routing tracks for data-path signals are also prepared in our architecture. Finally, our switch boxes for data-path tracks can be configured from user circuits, enabling efficient implementation of user-controlled multiplexers. Implementation of user circuits on the proposed architecture is supported by a set of our naive mapping tools, and they were used to implement several benchmark circuits for performance comparisons between the proposed architecture and the conventional fine grained architecture. In an experimental evaluation, the throughput of communication-oriented circuits was 2—3 times higher in our architecture than in its fine grained counterpart.