CMOS analog front-end IC for EEG applications with high powerline interference rejection

摘要

This paper presents a CMOS low-power analog front-end (AFE) circuit for EEG applications and research beyond the standard clinical relevant frequency range. The instrumentation amplifier (IA) is developed using operational transconductance amplifiers (OTA) as resistive load for gain adjustment. The lowpass notch filter (LPNF) has a capacitor programmable circuit that, due to the powerline interefence, selects between cutting 50 or 60 Hz signals. The AFE subcircuit consumes only 750 nW with 1 V supply, and attenuates over 50 dB at the notch cutoff frequencies. The circuit was designed in 0.13 μm CMOS technology and simulated on CADENCE (Virtuoso Analog Design Environment), showing good performance processing the noise in acquired EEG signals.