Multi-operand logarithmic addition/subtraction based on Fractional Normalization

摘要

This paper presents a method for adding several numbers represented in the Logarithmic Number System (LNS). The proposed technique is based on the normalization towards the largest input number. The distinct steps of the original two-input addition/subtraction using Fractional Normalization method (FN) [1] are modified in order to achieve performance and reduce hardware requirements. Three multi-operand adders are analyzed and compared: The first architecture uses the original FN method, the second one uses an introduced two-step modified FN (MFN) method, and the third architecture uses full MFN method. The proposed multi-operand adders are synthesized and evaluated for complexity and performance using a 65-nm 0.9V UMC CMOS library, for the cases of 4, 8, 16 inputs and an 11-bit word length.