formal specification; multiprocessing systems; pipeline processing; program verification; software architecture; μhb graph; O3 pipeline; OpenSPARC T2; PipeCheck; architectural specification; architecturally-specified consistency model; architecture-level analysis techniques; formal architecture-level definitions; gem5 simulator; memory consistency models; memory instruction; memory location; microarchitectural enforcement specification; microarchitectural enforcement verification; microarchitectural optimizations; microarchitecturally-happens-before graph; microarchitecture space; open-source pipelines; pipeline stage; preserved-program order; speculative load reordering; Buffer storage; Load modeling; Mathematical model; Microarchitecture; Pipelines; Program processors; Radio frequency;
机译:验证内存一致性模型的正确微体系结构实施
机译:通过模型检查来验证共享内存多处理器上的顺序一致性
机译:CheckFence:检查宽松内存模型上并发数据类型的一致性
机译:管道检查:指定和验证内存一致性模型的微架立强制
机译:指定,验证和在内存一致性模型之间进行转换。
机译:向量验证方法中一致性检查的使用
机译:针对弱内存模型的共享内存一致性协议验证:通过模型检查进行细化