A 0.36 pJ/bit, 12.5 Gb/s forwarded-clock receiver with a sample swapping scheme and a half-bit delay line

摘要

A 12.5Gb/s forwarded clock receiver based on a DLL with a bang-bang PD is presented. The stuck locking is detected and averted by swapping edge and data samples at the output of the PD. Moreover, required delay range of the VCDL is reduced by half with the proposed sample swapping scheme. The prototype chip exhibits the power efficiency of 0.36pJ/bit and occupies 0.025mm. Due to the wide jitter tracking bandwidth of DLL and the inherent jitter correlation between data and forwarded clock, the proposed receiver exhibits outstanding jitter tolerance whose corner frequency is higher than 300 MHz.