Aging and performance sensor for SRAM

摘要

CMOS memories occupy a significant percentage of the Integrated Circuits footprint. With the development of new manufacturing technologies to a smaller scale, performance and reliability challenges exist, namely caused by parametric variations such as Process variations (P), power supply Voltage (V) and Temperature (T), and Aging (A) or, in a general perspective, PVTA variations. The purpose of this paper is to present an aging and performance sensor, for CMOS memory cells, namely for SRAM cells, sensing and signaling performance degradation caused e.g. by PVTA variations. The detection strategy consists on the active monitoring on the bit lines the read and write operations performed by the memory cell. In the presence of PVTA degradations, read and write operations have slower transitions, which indicate performance degradation, thus increasing the probability of error occurrence. Hence, when transitions do not occur during the expected time frame, an error signal is flagged to the output due to a slow transition. The sensors' correct operation is demonstrated using SPICE simulations for 65nm and 22nm technologies, allowing to show their effectiveness on monitoring performance and aging degradation on SRAM memory blocks.